An error correction code (ECC) failure in a NAND flash memory triggers a sequence of reads, also referred to as hard bit reads (HBRs), until the read data is recovered. If an error occurs, multiple HBRs are performed to determine the soft bit information to use for decoding. Current techniques require that the HBR information from multiple iterations be buffered to determine the soft bit information from statistics on the multiple read retries. Low Density Parity Check (LDPC) error correction algorithms have been utilized for NAND flash memory, but may result in high read latency. LDPC error correction techniques require the use of soft bit information that is generated during different read iterations based on statistics of previous reads performed during the error recovery, which requires buffering of the hard bit read (HBR) information.
There is a need in the art for improved techniques for gathering soft bit information for error recovery operations in non-volatile storage devices.